1. Field of the Invention
Embodiments of the invention generally relate to measuring spatial plating cell current distribution represented by measuring the differential voltages inside an electrochemical plating cell in-Situ.
2. Description of the Related Art
In semiconductor processing, electrochemical plating (ECP) is generally the preferred technique for filling features formed onto substrates with a conductive material. A typical ECP process generally includes immersing a substrate into an electrolyte solution that is rich in ions of the conductive material (generally copper), and then applying an electrical bias between a conductive seed layer formed on the surface of the substrate and an anode positioned in the electrolyte solution. The application of the electrical bias between the seed layer and the anode facilitates an electrochemical reaction that causes the ions of the conductive material to plate onto the seed layer.
However, with conventional ECP processes and systems, the conductive seed layer formed on the substrate is generally very thin, and as such, is highly resistive. The resistive characteristics of the seed layer causes the electric field traveling between the anode and the seed layer in a plating process to be much more dense near the perimeter of the substrate where electrical contact with the seed layer is generally made. This increased electric field density near the perimeter of the substrate causes the plating rate near the perimeter of the substrate to increase proportionally. This phenomenon is generally known as the “terminal effect”, and is an undesirable characteristic associated with conventional plating systems.
The terminal effect is of particular concern to semiconductor processing, because as the size of features continues to decrease and aspect ratios continue to increase, the seed layer thickness will inherently continue to decrease. This decrease in the thickness of the seed layer will further increase the terminal effect, as the decreased thickness of the seed layer further increases the resistivity of the layer.
Another challenge in an electrochemical process is that features on some portions of a substrate may be undesirably filled or even filled up while immersing the substrate into a plating bath. During the immersion process, a forward or plating bias is generally applied to counteract etching of the seed layer on the substrate by the plating solution, which is generally an acidic solution. During this time period, which may be as little as 0.25 seconds, some features in certain region on the substrate may be filled which may result in poor uniformity and variable device yield performance.
Therefore, there is a need for an electrochemical plating cell and methods for plating onto conductive materials semiconductor substrates, wherein the plating thickness profile is monitored and controlled in real time.